1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to the formation of metallization layers and metal lines in which copper is used as the metallization metal.
2. Description of the Related Art
In the semiconductor industry, there is an ongoing effort to steadily increase the number of devices per unit area that may be fabricated of an appropriate substrate. Thus, current minimum feature sizes of approximately 0.2 xcexcm and less are realized with the prospect of 0.1 xcexcm in the near future. The decrease in feature size of the semiconductor devices allows the provision of increased integration density of the integrated circuits along with an improved device performance obtained by the size reduction of the individual elements, such as field effect transistors. The enormous number of semiconductor elements formed on a single chip area, however, reduces the available space for, and hence the cross-section of, metallization lines connecting these individual semiconductor elements. Although the feature size of the individual elements is reduced, the increased functionality and complexity of integrated circuits requires, on the other hand, a huge number of interconnect lines electrically connecting the individual circuit elements to provide for the required functionality. Due to the large number of interconnections required, which are provided in modern integrated circuits by a plurality of so-called metallization layers stacked on top of each other, the effective line length does not necessarily decrease in the same manner as the cross-sectional area of the lines is reduced, so that, in consequence, the electrical resistance in the interconnect lines increases, thereby partially offsetting the advantages obtained by reducing the feature sizes of the individual circuit elements. Consequently, the signal performance of modern integrated circuits may become restricted by the signal propagation delay caused by the interconnect lines rather than by the electrical characteristics of the individual circuit elements.
To reduce any parasitic RC time constants generated by the electrical resistance of the interconnect lines and the capacitance formed between adjacent lines, semiconductor manufacturers are increasingly tending to replace the most commonly used metal, aluminum, with a conductive material having a lower specific resistance. In this respect, copper has proven to be a viable candidate for metallization lines in ultra high density integrated circuits. Copper is an attractive substitute for standard aluminum lines and plugs, since copper films exhibit a much higher electromigration and stress void resistance than do aluminum films. However, the processing of copper in a semiconductor production line is extremely difficult, since patterning and etching of copper films is substantially impractical at lower process temperatures, making it more advantageous to deposit copper films into recesses of previously patterned dielectric layers and then to remove the excess metal by chemical mechanical polishing (CPM). This technique of forming metallization layers is also often referred to as damascene technique. A further disadvantage in using copper layers is the copper""s characteristic to immediately form corrosion and discoloration at the surface upon exposure to a reactive, i.e., oxygen-containing ambient. Since corrosion and discoloration on the surface may lead to an insufficient adhesion to adjacent materials and to a deteriorated surface resistance, commonly, the copper is cleaned after exposure to an oxidized ambient and a cap layer is provided immediately after the cleaning process to passivate the metallization layer, thereby improving adhesion of the copper to adjacent materials and enhancing the long term stability of the metallization layer.
To this end, typically a capping layer, for example, a silicon nitride layer, is formed after cleaning the copper surface that has been exposed by a preceding chemical mechanical polishing process. A typical known process flow for fabricating a copper line with a capping layer in a damascene metallization structure may comprise the following steps.
After the recesses are formed in a dielectric layer, one or more seed layers are deposited over the structure for a subsequent electroplating deposition of copper. The one or more seed layers may also act as a barrier and adhesion layer to the adjacent dielectric layer. Alternatively, a separate barrier metal layer, e.g., tantalum, may be formed over the dielectric layer and in the recesses therein. Thereafter, a copper seed layer may be formed above the barrier metal layer.
Subsequently, bulk copper is deposited by electroplating to thereby fill the recesses in the dielectric layer. Thereafter, the excess material is removed by a CMP process. Thus, the planarized surface of the semiconductor structure comprises surface portions of copper as well as surface portions of dielectric material. Next, a cleaning treatment, by means of a reactive plasma, is performed to remove corrosion and discoloration, primarily consisting of copper oxide, formed on the exposed copper surface during and after the CMP procedure. The substrate is exposed to an ambient comprising nitrogen (N2), ammonia (NH3) and silane (SiH4), which are continuously fed into a reaction chamber at a predefined flow rate for a predefined time interval, while a predefined pressure is maintained in the reaction chamber. Typical process parameters for this process may be as follows. All three gases are supplied to the reaction chamber for approximately 15-70 seconds with the substrate temperature maintained at approximately 400xc2x0 C. In this way, discoloration and corrosion are reduced at the copper surface. Following this cleaning sequence, possibly interrupted by an additional purging step, nitrogen and silane is introduced into the reaction chamber to form a silicon nitride capping layer on top of the cleaned copper surface. Although the copper surface passivated in the manner as described above significantly relaxes the problems involved in forming reliable copper metallization layers, it turns out that the copper surface area of the copper line gives rise to another serious issue when feature sizes are steadily decreasing. With a reduced cross-sectional area, as required in sophisticated integrated circuits, the current densities within the metallization lines significantly increase and, even for copper lines with their superior characteristics compared to aluminum lines, an intolerable degree of electromigration is observed, resulting in a reduced reliability of the integrated circuit. In particular, the surface area of the copper line covered by the capping layer has been identified as one major electromigration path at higher current densities and increased temperatures.
In view of the above problems regarding the passivation of copper lines and the issues involved in increased electromigration of copper lines of reduced cross-sectional areas, a need exists for a new improved technique for protecting a copper surface during the manufacturing of a device and during the operation at elevated current densities and temperatures.
Generally, the present invention is based on the inventors"" finding that electromigration on a copper surface can be effectively suppressed by forming a copper/silicon film at the surface, wherein the copper/silicon film may then be passivated by providing a corresponding capping layer, such as a silicon nitride layer.
According to one illustrative embodiment of the present invention, a method of protecting a copper surface in a semiconductor device comprises providing a substrate having formed thereon a dielectric layer with a recessed portion and copper structure positioned in the recessed portion, wherein the copper structure has at least one exposed copper surface. A first reactive plasma environment is created that comprises nitrogen and ammonia and the copper surface is exposed to the first reactive plasma environment for a first time interval. Subsequently, a second reactive plasma environment is created that comprises nitrogen, ammonia and a gaseous compound including silicon. Finally, the copper surface is exposed to the second reactive plasma environment for a second time interval that is shorter than the first time interval.
According to a further illustrative embodiment of the present invention, a method of protecting a copper surface in a semiconductor device comprises providing a substrate having formed thereon a dielectric layer having a recessed portion and copper structure positioned in the recessed portion, wherein the copper structure has at least one exposed copper surface. Next, the exposed copper surface is cleaned and a copper/silicon film is formed on the cleaned copper surface in situ.
According to yet another embodiment of the present invention, a semiconductor device, including a metallization structure, comprises a substrate including at least one copper structure, wherein the at least one copper structure has at least one copper surface with a copper/silicon film formed thereon.